1. Profiling High Level Abstraction Simulators of Multiprocessor Systems (WCAS 2012)
  2. Optimizing Simulation in Multiprocessor Platforms using Dynamic-Compiled Simulation (WSCAD-SSC 2012)


  1. Software Co-Verification Based on Program Traces from Different Processors (WISH 2011)
  2. Using Multiple Abstraction Levels to Speedup an MPSoC Virtual Platform Simulator (RSP 2011)


  1. Optimizing a Retargetable Compiled Simulator to Achieve Near-Native Performance (WSCAD-SSC 2010)(in Portuguese)
  2. ARP: Um Gerenciador de Pacotes para Sistemas Embarcados com Processadores Modelados em ArchC (WSE 2010)(in Portuguese)


  1. Dotando ArchC com Infraestrutura para Geracao de Montadores e Simuladores ARM (WSCAD-WIC)(in Portuguese)
  2. Um Sistema de Ligacao Dinamica Independente de Arquitetura Baseado em ADL (IC-TEC-REP)(in Portuguese)


  1. An Open-Source Binary Utility Generator (ACM TODAES)


  1. A Multi-Model Power Estimation Engine for Accuracy Optimization (ISLPED 2007)
  2. An Efficient Framework for High-Level Power Exploration (MWSCAS 2007)
  3. A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation (RSP 2007)
  4. A Methodology and Toolset to Enable SystemC and VHDL Cosimulation (ISVLSI 2007)
  5. Automatic Retargeting of Binary Utilities for Embedded Code Generation (ISVLSI 2007)
  6. On the Limitations of Power Macromodeling Techniques (ISVLSI 2007)
  7. PowerSC: A SystemC Framework for Power Estimation (NASCUG).
  8. PowerSC: A SystemC-based framework for power estimation(IC-TEC-REP)
  9. Estimativa de Consumo de Energia em Nivel de Instrucao para Processadores Modelados em ArchC (Master Dissertation)(in Portuguese)


  1. Clustering-Based Microcode Compression
  2. 2D-VLIW: An Architecture Based on the Geometry of Computation
  3. Dual Selective Code Compression
  4. Exploiting Dynamic Reconfiguration Techniques: The 2D-VLIW Approach
  5. The Datapath Merging Problem in Reconfigurable Systems: Complexity, Dual Bounds and Heuristic Evaluation
  6. Software-Based Transparent and Comprehensive Control-Flow Error Detection
  7. The 2D-VLIW Architecture
  8. Projeto e Desenvolvimento de Sistemas Embarcados Multiprocessados(in Portuguese)


  1. The ArchC Architecture Description Language and Tools (Springer JDAES)
  2. Extending the ArchC Language for Automatic Generation of Assemblers (SBAC-PAD)
  3. Geracao Automatica de Montadores para Modelos de Arquiteturas Escritos em ArchC (in Portuguese)


  1. ArchC: A SystemC-Based Architecture Description Language (SBAC-PAD)
  2. Modeling and Simulating Memory Hierarchies in a Platform-based Design Methodology (DATE)
  3. Optimizations for Compiled Simulation Using Instruction Type Information (SBAC-PAD)
  4. Teaching Computer Architecture Using an Architecture Description Language (WCAE)


  1. Emulating Operating System Calls in Retargetable ISA Simulators
  2. Exploring Memory Hierachy with ArchC (SBAC-PAD)
  3. The ArchC Architecture Description Language